Power dissipation and energy consumption are key parameters in designing embedded systems, such as cellular telephones, personal digital assistants (PDA), and multi-feature smart devices. These parameters are not only important for increasing battery life, they are important for reducing integrated device packaging costs and device cooling costs.
Reduced instruction set computing (RISC) architectures, such as million instructions per second (MIPS) machines and Advanced RISC machines (ARM), enjoy great popularity in the embedded systems market and, as a result, benefit from power and energy consumption management. The Intel XScale™ core architecture, available from Intel Corporation of Santa Clara, Calif., is an example implementation of the ARM architecture. XScale™-based processors are used in the Intel Personal Internet Client Architecture (PCA) processors (e.g., PXA250, PXA261, and PXA262) employed in vast numbers of embedded systems.
Power and energy management in processor architectures can be done at several levels within an embedded system hierarchy, including, the integrated circuit component level, the platform level, the operating system level, the managed runtime environment level, the application level, and the user level. In most systems, power and energy management is performed by the operating system. Some operating systems, for example, use dynamic frequency and voltage scaling techniques.
Frequency scaling is a technique where the processor clock is adjusted by a multiple of the maximum clock frequency or the memory bus frequency. This permits the processor to consume less power, but does so at the expense of reduced performance. Frequency scaled processors can have any number of discrete operating frequency points. For example, the Intel PXA250 processor supports the following operating frequencies in run mode: 99.5 MHz at 0.85V; 118, 132.7, 147.5,165.9, and 199.1 MHz at 1.0V; 235.9, 265.4, and 294.9 MHz at 1.1V; and 381.9 MHz at 1.3V.
Dynamic voltage scaling reduces the power consumed by a processor by lowering its operating voltage. A reduction in operating voltage also requires a proportional reduction in frequency. Voltage scaling is preferred because the dynamic power consumed by a CMOS processor is directly proportional to the square of the operating voltage: P(power)=C(capacitance)*V2 (voltage2)*f(frequency), where C is the average switching capacitance loading of the processor, f is the operating frequency, and V is the supply voltage. Power consumption can be minimized by reducing C, f, or V. Reducing voltage will have a quadratic effect on power. By varying the voltage and the frequency, it is possible to obtain more than a quadratic reduction in power dissipation. Scaling down frequency without scaling voltage is typically not done, however, since the power savings is offset by the increase in execution time, yielding no reduction in the total amount of energy consumed.
The dynamic voltage and frequency scaling techniques executed in operating systems today use interval-based schedulers. Although prevalent, interval-based schedulers have numerous shortcomings.
One shortcoming is that interval-based schedulers merely predict a future workload. They use algorithms based on uniform-length intervals (in the range of 30 to 100 ms) to monitor the processor utilization of a previous interval. That historical data is then used to set the voltage level for the next interval. Although the interval-based scheduling algorithm is simple and easy to implement, it often predicts the future workload incorrectly, especially when an application's workload exhibits large variability, e.g., cycle to cycle variability. Interval-based schedulers are unable to scale the voltage and frequency of the processor at runtime based on actual usage patterns of the executing application.
A second shortcoming is that interval-based schedulers predict usage based on a processor utilization factor unrelated to future workload. And there is no standardization by which that utilization factor can be made to accurately predict future workload.